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ADE7761B
Parameter
Value
Unit
Test Conditions/Comments
LOGIC INPUTS 5
PGA, SCF, S1, and S0
Input High Voltage, V INH
Input Low Voltage, V INL
Input Current, I IN
Input Capacitance, C IN
2.4
0.8
±3
10
V, min
V, max
μA, max
pF, max
V DD = 5 V ± 5%
V DD = 5 V ± 5%
Typical 10 nA, V IN = 0 V to V DD
LOGIC OUTPUTS 5
CF, REVP, and FAULT
Output High Voltage, V OH
Output Low Voltage, V OH
4
1
V, min
V, max
V DD = 5 V ± 5%
V DD = 5 V ± 5%
F1 and F2
Output High Voltage, V OH
Output Low Voltage, V OH
POWER SUPPLY
V DD
I DD
4
1
4.75
5.25
3.65
V, min
V, max
V, min
V, max
mA, max
V DD = 5 V ± 5%, I SOURCE = 10 mA
V DD = 5 V ± 5%, I SINK = 10 mA
For specified performance
5 V ? 5%
5 V + 5%
1
2
3
4
5
See plots in the Typical Performance Characteristics section.
See the Terminology section for explanation of specifications.
See the Fault Detection section for explanation of fault detection functionality.
See the Missing Neutral Detection section for explanation of missing neutral detection functionality.
Sample tested during initial release and after any redesign or process change that might affect this parameter.
TIMING CHARACTERISTICS
V DD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, on-chip oscillator, T MIN to T MAX = ?40°C to +85°C. Sample tested during
initial release and after any redesign or process change that might affect this parameter. See Figure 2.
Table 2.
Parameter
t 1 1
t 2
t 3
t 41
t 5
t 6
Value
120
See Table 8
1/2 t 2
90
See Table 8
CLKIN/4
Unit
ms
sec
sec
ms
sec
sec
Test Conditions/Comments
F 1 and F 2 pulse width (logic high)
Output pulse period (see the Transfer Function section)
Time between F 1 falling edge and F 2 falling edge
CF pulse width (logic high)
CF pulse period (see the Transfer Function section)
Minimum time between F 1 pulse and F 2 pulse
1
The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See the Transfer Function section.
Timing Diagram
t 1
F1
t 6
t 2
F2
t 4
t 3
t 5
CF
Figure 2. Timing Diagram for Frequency Outputs
Rev. 0 | Page 4 of 24
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